1. Field of the Invention
The present invention relates to a buffer memory device for fixed-length packet data and a method of controlling the buffer memory device.
2. Description of the Related Art
An example of a network wherein voice data or the like are transmitted in packet units, is shown in FIG. 1. In the drawing, the network includes multiplex lines 1, packet exchanges 2A, 2B and 2C, packet terminals 3A to 3C, exchanges 4A to 4C and telephone sets 5A to 5C. A voice signal input to, for example, the packet terminal 3A is encoded and then resolved into predetermined unit data in the packet terminal 3A so that each of the predetermined data units is attached with a party destination data to prepare a packet. The packets thus prepared are transmitted through the packet exchanges 2A to 2B to the party packet terminal 3B.
FIG. 2 is a block diagram showing an interior arrangement of each of the packet exchanges 2A to 2C, which includes terminal interfaces TINFs provided as connected to associated packet terminals, a line interface LINF connected to multiplex lines 1, a controller CONT, a bus access controller ARB, an interrupt control bus BUS1, a control bus BUS2, an access control bus BUS3 and a data bus BUS4. The terminal interface TINF, when receiving a calling packet from the packet terminal connected thereto, sends an interrupt command through the interrupt control bus BUS1 to the controller CONT. The controller CONT, when confirming the received interrupt command, has access to a memory (not shown) provided within the terminal interface TINF to confirm the calling data (destination number, window size and so on). Thereafter, the controller CONT outputs an access request to the data bus BUS4 onto the access control bus BUS3 to transmit a connection request packet to the party packet terminal which forms an opposing node. When having acquired the data bus access authority, the controller CONT sends the connection request packet to the line interface LINF through the data bus BUS4. The line interface LINF itself, when receiving the connection request packet, prepares the connection request packet in the same manner as for the data packet and transmits it onto the multiplex line 1. In response to it, when the line interface LINF receives a connection approval or disapproval packet from the party packet terminal of the opposing node, the line interface sends the received packet to the controller CONT. The controller CONT, when receiving, for example, the connection approval packet, prepares a connection table in a memory (not shown) in the line interface LINF and the terminal interface TINF and sends the connection approval packet to the terminal interface TINF through the control bus BUS2. The terminal interface TINF responsive to the reception of the connection approval packet, transmits the packet to the associated packet terminal and thereafter is put in a data transmission phase. In the data transmission phase, the terminal interface TINF sends the data packet to the line interface LINF. In this case, the transmitted data packet comprises a data part D attached with header part H as shown in FIG. 3. The line interface LINF receiving the data packet stores it in the buffer and then transmits it to the multiplex line 1. The above operation is similarly repeated even for the data packet in the data transmission phase. In the case of a disconnection, i.e., the connection disapproval packet, the same operation as in the connection request is carried out except that the connection table is deleted.
Shown in FIG. 4 is an internal arrangement (illustrating only packet or signal transmission directions to a multiplex line) of the line interface LINF which includes a data bus interface 4, an address coincidence detector (address filtering) 5, a packet distributor part 6, packet queues 7-1 to 7-n arranged in a plurality of rows and stored in a buffer memory BM, a transmission packet decider 8, and a line interface 9. The data bus interface 4, which forms an interface with the data bus BUS4 in FIG. 2, performs packet transmission and reception to and from the data bus BUS4 in accordance with the timing of the data bus BUS4. The address coincidence detector 5 compares the destination address of the received packet with its own address, sends the received packet to the packet distributor 6 when finding an address coincidence therebetween, and otherwise discards it. The packet distributor 6 determines, on the basis of the data in the header part H of the received packet, one of the packet queues 7-1 to 7-n in which the received packet is to be arranged. The data in the header part H include data relating to connection, priority associated with transmission delay, etc. On the basis of, for example, the priority data among these data, the packet distributer 6, distributes the received packet to one of the packet queues 7-1 to 7-n. The transmission packet decider 8 determines one of the packet queues 7-1 to 7-n from which a packet is to be taken out. The decision of the decider 8 is made by taking account of the priority, the number of staying packets in the packet queues and the past control totally. The line interface 9, which forms an interface with the multiplex line 1, transmits the decided packet to the multiplex line 1 in synchronism with the clock of the line 1.
Referring to FIG. 5, there is shown a configuration of one, for example, 7-1 of the packet queues 7-1 to 7-n, which inlcudes a two-port RAM 10 having two ports A and B, a write data bus 11, a read data bus 12, a port-A-side address bus 13, a port-B-side address bus 14, a write request 15, a read request 16, a port-A-side address pointer 17, a port-B-side address pointer 18, an up/down counter (U/D counter) 19, a buffer controller 20, and access disable signals including a read disable signal 21R and a write disable signal 21W. Data access to the 2-port RAM 10 is carried out on a first-in first-out basis to read out data from the RAM in the sequence of written data.
With such an arrangement, the port-A-side address pointer 17, when receiving the write request 15, applies to a port-A-side address input terminal of the RAM 10 an address data indicative of the address (packet length interval) of an area of the RAM 10 in which writing is next to be realized, whereby the RAM 10 stores a packet received from the write data bus 11 in the area specified by the address data received from the pointer 17. Like the pointer 17, the port-B-side address pointer 18, when receiving the read request 16, similarly applies to a port-B-side address input terminal of the RAM 10 an address data indicative of the address (packet length interval) of an area of the RAM 10 from which reading is next to be realized, whereby the RAM 10 reads out a packet from the area specified by the address data received from the pointer 18 and outputs the read packet onto the data bus 12. The U/D counter 19, when receiving the write request 15, increments its count value by "1" while, when receiving the read request 16, the counter decrements its count value by "1" , so that the count value indicates the number of staying packets in the packet queue 7-1. Thus, when the count value of the counter 19 becomes "1", the controller 20 judges that the number of staying packets in the queue 7-1 became "0", and outputs the read disable signal 21R to inhibit the reading of packets from the queue 7-1. When the count value of the counter 19 becomes a predetermined maximum, the controller 20 judges that the queue 7-1 is full of packets and outputs the write disable signal 21W to inhibit the writing of any packets.
Such an arrangement of the buffer memory BM as mentioned above has a problem in that, taking into consideration the fact that packets may be concentrated on a specific one of the packet queues, the capacity of the RAM 10 is determined so that the queues can have a relatively large length, which results in one of the queues being used infrequently which is uneconomical.